Conventionally, an active-matrix liquid crystal display device including retention capacitor wires has been known to have such a problem that in a case where reverse polarity driving is carried out, an even display cannot be obtained at the time of turning on of power (i.e., in the initial period). This is because the retention capacitor wires are supplied with power potentials that become indefinite immediately after the liquid crystal display device has been turned on.
A technique for solving such a display problem at the time of turning on of power is disclosed, for example, in Patent Literature 1. FIG. 25 is a block diagram schematically showing a configuration of a liquid crystal display device of Patent Literature 1.
The liquid crystal display device includes: data signal lines S1 to Sn provided on a glass substrate and arranged along a second direction; scanning signal lines G1 to Gn provided on the glass substrate and arranged along a first direction; pixel TFTs (transistors) 1 each provided in an area near a point of intersection between a data signal line and a scanning signal line; auxiliary capacitors (retention capacitors) C1 each connected to a drain terminal of a pixel TFT 1; pixel electrodes 2 each connected to a drain terminal of a pixel TFT 1; liquid crystal capacitors C2 each formed between a pixel electrode 2 and a counter electrode 3 disposed opposite the pixel electrode 2 with a liquid crystal layer sandwiched therebetween; a scanning line driving circuit (scanning signal line driving circuit) 4, which drives the scanning lines (scanning signal lines); a source driver (data signal line driving circuit) 5, which drives the data signal lines; auxiliary capacitor power supply lines (retention capacitor wires) CS1 to CSn each connected to an end of each one of a row of auxiliary capacitors C1 arranged along the scanning lines (along the second direction); and an auxiliary capacitor power supply selection circuit (retention capacitor wire driving circuit) 6, which sets the potentials of the auxiliary capacitor power supply lines CS1 to CSn.
FIG. 26 is a circuit diagram showing a configuration of the auxiliary capacitor power supply selection circuit 6 in detail. As shown in FIG. 26, the auxiliary capacitor power supply selection circuit 6 has a PMOS transistor 9, which selects whether or not to supply a first reference potential VcsH to the auxiliary capacitor power supply lines CS1 to CSn, and an NMOS transistor 8, which selects whether or not to supply a second reference potential VcsL (<VcsH) to the auxiliary capacitor power supply lines CS1 to CSn, and these transistors 8 and 9 are turned on/off under control of an AND gate 10 provided in the scanning line driving circuit 4.
The AND gate 10 calculates the logical product of (i) a power-on power supply control signal s1 for controlling the potentials of the auxiliary capacitor power supply lines CS1 to CSn at the time of turning on of power and (ii) a polarity-reversal power supply control signal s2 for controlling the potentials of the auxiliary capacitor power supply lines CS1 to CSn at the time of polarity reversal, and on the basis of a result of the calculation, switches between turning on and off the transistors 8 and 9.
In this configuration, during a predetermined period of time after the time of turning on of power, the power-on power supply control signal s1 is at a low level (0 V), whereby an output from the AND gate 10 (see FIG. 26) in the scanning line driving circuit 4 is at a low level and the PMOS transistor is turned on, with the result that the auxiliary capacitor power supply lines CS1 to CSn are supplied with the first reference voltage VcsH. Since the first reference voltage VcsH is higher than the second reference potential VcsL, the potentials of all of the auxiliary capacitor power supply lines CS1 to CSn are high during the predetermined period of time after the time of turning on of power. When the potentials of the auxiliary capacitor power supply lines CS1 to CSn are high, the potential of each pixel electrode 2 is also relatively high, and the end-to-end potential of each liquid crystal capacitor C2 (i.e., the difference in potential between the counter electrode 3 and each pixel electrode 2) is small. With this, for example, a normally white liquid crystal display device (which carries out a white display when no signal is applied) carries out a display close to a white display even when it is turned on, with the result that no bright line can be seen. After that, after passage of the predetermined period of time, the auxiliary capacitor power supply selection circuit 6 of FIG. 26 raises the power-on power supply control signal s1 to a high level. This causes the logic of the AND gate 10 to change in accordance with the logic of the polarity-reversal power supply control signal s2. Accordingly, the turning on and off of the NMOS transistor 8 and PMOS transistor 9 changes in accordance with the cycle of reverse polarity driving. This causes the potentials of the auxiliary capacitor power supply lines CS1 to CSn to the first reference voltage VcsH or the second reference voltage VcsL in accordance with the cycle of reverse polarity driving.
Thus, in the configuration, since, during a predetermined period of time after the time of turning on of power, all of the auxiliary capacitor power supply lines CS1 to CSn is set to an identical power supply potential (first reference voltage), there is no variation in potential level among the auxiliary capacitor power supply lines CS1 to CSn. This allows elimination of a problem with a display at the time of turning on of power.